CAJ | 학술논문

基于数字化模拟电路设计技术和自适应动态反馈方法设计了一个高速串行接收器,包含采样放大器、时钟发生电路、匹配电阻电路.后两者的精度直接决定了接收器性能.采用TSMC的CMOS 0.25μm混合信号模型,在Cadence软件环境下用spectre仿真器进行模拟.结果表明,时钟发生电路输出的五相时钟间隔0.416 ns,抖动35 ps,锁定时间1.8 μs;匹配电阻阻值波动在44.3～45.6 Ω,稳定时间6μs,平均误差±1.45%,最大误差1.56%.联调后整个接收器电路具有接收480 Mbps高速串行数据的能力.
기우수자화모의전로설계기술화자괄응동태반궤방법설계료일개고속천행접수기,포함채양방대기、시종발생전로、필배전조전로.후량자적정도직접결정료접수기성능.채용TSMC적CMOS 0.25μm혼합신호모형,재Cadence연건배경하용spectre방진기진행모의.결과표명,시종발생전로수출적오상시종간격0.416 ns,두동35 ps,쇄정시간1.8 μs;필배전조조치파동재44.3～45.6 Ω,은정시간6μs,평균오차±1.45%,최대오차1.56%.련조후정개접수기전로구유접수480 Mbps고속천행수거적능력.
The receiver is central module in serial link. Involved in digital-based analog circuit-design technology and negative-feedback dynamic adjustment method, this paper brings forward a high speed serial receiver, which consists of sampling-amplifier, clock-generator, matching resistor. The latter two parts determine performance of receiver. Using Cadence's SPECTRE software and TSMC's library of 0.25 um mixedsignal CMOS model, simulation results revealed that the clock-generator produces five 480Mbps equal-spaced clock signals between one another. Time interval between each other keeps 0. 416 ns with jitter of 35 ps, lock time of 1.8 μs; the value of resistor rangs within [44.3 Ω,45.6 Ω] , maximum time leveling off is less than 6 μs, average error is ± 1.45% , maximum error range within 1.56%. Altogether the whole receiver possess capacity in receiving 480 Mbps serial data.