计量学报
計量學報
계량학보
ACTA METROLOGICA SINICA
2010年
2期
145-149
,共5页
计量学%原子钟%锁相环路%数字正交解调%FPGA
計量學%原子鐘%鎖相環路%數字正交解調%FPGA
계량학%원자종%쇄상배로%수자정교해조%FPGA
Metrology%Atomic clock%Phase locked loop%Digital quadrature demodulation%FPGA
介绍了将数字正交解调算法应用于CPT原子钟系统的锁相环路,通过FPGA硬件结构实现解调功能所开展的研究.经MATLAB和QUARTUS2的联合仿真表明,该算法抗噪声能力强,解调结果可靠性高,是应用于高性能CPT原子钟的理想算法.实际应用于CPT原子钟的实验结果与理论预期和实验仿真结果相一致.该方案有利于原子频标的工作状态调整和保持产品性能一致性.
介紹瞭將數字正交解調算法應用于CPT原子鐘繫統的鎖相環路,通過FPGA硬件結構實現解調功能所開展的研究.經MATLAB和QUARTUS2的聯閤倣真錶明,該算法抗譟聲能力彊,解調結果可靠性高,是應用于高性能CPT原子鐘的理想算法.實際應用于CPT原子鐘的實驗結果與理論預期和實驗倣真結果相一緻.該方案有利于原子頻標的工作狀態調整和保持產品性能一緻性.
개소료장수자정교해조산법응용우CPT원자종계통적쇄상배로,통과FPGA경건결구실현해조공능소개전적연구.경MATLAB화QUARTUS2적연합방진표명,해산법항조성능력강,해조결과가고성고,시응용우고성능CPT원자종적이상산법.실제응용우CPT원자종적실험결과여이론예기화실험방진결과상일치.해방안유리우원자빈표적공작상태조정화보지산품성능일치성.
The study of applying digital quadrature demodulation algorithm to phase locked loop of CPT atomic clock realized with a FPGA core is presented Simulation results for this scheme with both MATLAB and QUARTUS2 reveal its good noise resisting property and reliable demodulation ability Therefore, it is an ideal scheme for high performance CPT atomic clock Experimental result of application the scheme to CPT atomic clock consists with that from simulation This scheme makes it easier to modify the operation state of atomic clock and keeps better consistency of products.
