微电子学
微電子學
미전자학
MICROELECTRONICS
2010年
2期
230-234
,共5页
源耦合逻辑(SCL)%TSPC%双模分频器%多模分频器%频率合成器
源耦閤邏輯(SCL)%TSPC%雙模分頻器%多模分頻器%頻率閤成器
원우합라집(SCL)%TSPC%쌍모분빈기%다모분빈기%빈솔합성기
Source-coupled logic%TSPC%Dual-modulus divider%Multi-modulus divider%Frequency synthesizer
提出了一种基于新型源耦合逻辑或门的双模分频器和一种基于双D触发器的双模分频器.与传统的基于与门逻辑的双模分频器相比,基于新型源耦合逻辑的双模分频器减少了一级堆叠管,增加了采样开关管的过驱动电压,提高了工作速度.基于双D触发器的双模分频器比传统的基于4个D触发器的双模分频器节省近一半的晶体管,减小了芯片面积,降低了多模分频器的功耗.基于上述两种新型双模分频器架构,并引入分频比扩展技术,在0.18 μm CMOS工艺下,实现了一种宽工作范围高速低功耗的多模分频器,分频范围为4～8192,工作频率范围0.8～2.7 GHz,消耗电流1.25 mA.
提齣瞭一種基于新型源耦閤邏輯或門的雙模分頻器和一種基于雙D觸髮器的雙模分頻器.與傳統的基于與門邏輯的雙模分頻器相比,基于新型源耦閤邏輯的雙模分頻器減少瞭一級堆疊管,增加瞭採樣開關管的過驅動電壓,提高瞭工作速度.基于雙D觸髮器的雙模分頻器比傳統的基于4箇D觸髮器的雙模分頻器節省近一半的晶體管,減小瞭芯片麵積,降低瞭多模分頻器的功耗.基于上述兩種新型雙模分頻器架構,併引入分頻比擴展技術,在0.18 μm CMOS工藝下,實現瞭一種寬工作範圍高速低功耗的多模分頻器,分頻範圍為4～8192,工作頻率範圍0.8～2.7 GHz,消耗電流1.25 mA.
제출료일충기우신형원우합라집혹문적쌍모분빈기화일충기우쌍D촉발기적쌍모분빈기.여전통적기우여문라집적쌍모분빈기상비,기우신형원우합라집적쌍모분빈기감소료일급퇴첩관,증가료채양개관관적과구동전압,제고료공작속도.기우쌍D촉발기적쌍모분빈기비전통적기우4개D촉발기적쌍모분빈기절성근일반적정체관,감소료심편면적,강저료다모분빈기적공모.기우상술량충신형쌍모분빈기가구,병인입분빈비확전기술,재0.18 μm CMOS공예하,실현료일충관공작범위고속저공모적다모분빈기,분빈범위위4～8192,공작빈솔범위0.8～2.7 GHz,소모전류1.25 mA.
New dual-modulus dividers (DMD) based on new source-couple logic (SCL) "OR" gate and on dual D-type flip-flop were proposed. Compared with traditional DMD based on SCL "AND" gate, the novel SCL-based DMD eliminates a stage of stacking transistors to increase overdrive voltage of switching transistors and speed. A DMD based on dual D-type flip-flop was also introduced, in which number of transistors was reduced by about half, compared with quad D-type flip-flop architecture, and it also occupies smaller chip area and consumes less power. Based on the two DMDs and using division ratio extension technique, a high speed and low power multi-modulus divider (MMD) was implemented in 0.18 μm CMOS process, which had a division range from 4 to 8192, and an operating frequency range from 0.8 GHz to 2.7 GHz, with a current consumption of 1.25 mA.
