CAJ | 학술논문

描述了一种基于TSMC 0.25 μm CMOS工艺设计的10 Gbit/s(STM-64,OC-192)四相位时钟1:4分接器.为了实现最高的工作频率和抑制共模噪声,所有的电路都采用了源极耦合逻辑(SCFL)结构.本分接器的特点是通过采用固定延时缓冲来实现四相位时钟和输出边沿的对准.通过在晶圆测试,该芯片在输入10 Gbit/s 长度为231-1伪随机码流时,分接功能正确.此时所测得的眼图的均方根抖动、上升沿和下降沿分别为11,123和137 ps.芯片面积为0.9 mm×1.2 mm,在3.3 V单电源供电的情况下的典型功耗为550 mW.
묘술료일충기우TSMC 0.25 μm CMOS공예설계적10 Gbit/s(STM-64,OC-192)사상위시종1:4분접기.위료실현최고적공작빈솔화억제공모조성,소유적전로도채용료원겁우합라집(SCFL)결구.본분접기적특점시통과채용고정연시완충래실현사상위시종화수출변연적대준.통과재정원측시,해심편재수입10 Gbit/s 장도위231-1위수궤마류시,분접공능정학.차시소측득적안도적균방근두동、상승연화하강연분별위11,123화137 ps.심편면적위0.9 mm×1.2 mm,재3.3 V단전원공전적정황하적전형공모위550 mW.
A 10 Gbit/s (STM-64,OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock was achieved in TSMC s standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique.All of the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed and suppress common mode distortions.This DEMUX is featured by constant-delay buffers to generate a 4-phase clock and adjust skews of the four channel outputs.The fabricated DEMUX operates error free at 10 Gbit/s by 231-1 pseudorandom bit sequences (PRBS) via on-wafer testing.The measured root mean square (rms) jitter,rising and failing edge of the eye-diagram are 11,123 and 137 ps,respectively.The chip size is 0.9 mm×1.2 mm and the power dissipation is 550 mW with a 3.3 V supply.