CAJ | 학술논문

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.
제출료일충고속저공모적저압차분접구전로,타가이응용우CPU,LCD,FPGA등수요고속접구적심편중.재발송단,일개은정적삼고전압화공모반궤전로피응용우저압차분전로중,타사득발송단능구극복전원、온도이급공예인기적파형변화.재접수단채용료궤도궤적방대기결구,타정이공작도1.6Gb/s.심편설계가공채용적시0.18μm CMOS공예,심편측시결과표명,정개발송접수단수거전수속솔가이체도1.6Gb/s,동시발송화접수단적공모분별시35화6mW.
This paper describes the design of a low voltage differential signal (LVDS) transmitter and receiver with highspeed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable reference and acommon mode feedback circuit are integrated into the LVDS drivers, which enable the transmitter to tolerate variations ofprocess, temperature, and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture that allowsa 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3V,0.18μm CMOS technology. The ex-perimental results demonstrate that the transmitter and receiver reach 1.6Gb/s. The transmitter and receiver pad cells ex-hibit a power consumption of 35 and 6mW,respectively.