计算机工程与科学
計算機工程與科學
계산궤공정여과학
COMPUTER ENGINEERING & SCIENCE
2009年
z1期
80-83
,共4页
随机数生成器%多输出LFSR%FPGA
隨機數生成器%多輸齣LFSR%FPGA
수궤수생성기%다수출LFSR%FPGA
random number generator%multi-output LFSR%FPGA
本文系统地分析了多输出外部反馈LFSR方法产生均匀分布随机数的工作原理、变换矩阵的特点、产生随机数的周期以及LFSR的级数选择等问题,并提出了基于多输出外部反馈LFSR方法设计均匀分布随机数生成器的具体步骤.本文在Xilinx Vertex Ⅳ FPGA上设计实现的23级16位输出的LFSR型均匀分布随机数生成器仅消耗了36个Slices资源和23个Flip Flops资源,工作频率可以达到993MHz,相对于多LFSR复用的实现方式,节约了90%以上的硬件资源.并且,该生成器产生的随机数可以通过K-S检测方法的质量评估.
本文繫統地分析瞭多輸齣外部反饋LFSR方法產生均勻分佈隨機數的工作原理、變換矩陣的特點、產生隨機數的週期以及LFSR的級數選擇等問題,併提齣瞭基于多輸齣外部反饋LFSR方法設計均勻分佈隨機數生成器的具體步驟.本文在Xilinx Vertex Ⅳ FPGA上設計實現的23級16位輸齣的LFSR型均勻分佈隨機數生成器僅消耗瞭36箇Slices資源和23箇Flip Flops資源,工作頻率可以達到993MHz,相對于多LFSR複用的實現方式,節約瞭90%以上的硬件資源.併且,該生成器產生的隨機數可以通過K-S檢測方法的質量評估.
본문계통지분석료다수출외부반궤LFSR방법산생균균분포수궤수적공작원리、변환구진적특점、산생수궤수적주기이급LFSR적급수선택등문제,병제출료기우다수출외부반궤LFSR방법설계균균분포수궤수생성기적구체보취.본문재Xilinx Vertex Ⅳ FPGA상설계실현적23급16위수출적LFSR형균균분포수궤수생성기부소모료36개Slices자원화23개Flip Flops자원,공작빈솔가이체도993MHz,상대우다LFSR복용적실현방식,절약료90%이상적경건자원.병차,해생성기산생적수궤수가이통과K-S검측방법적질량평고.
Firstly,we analyze the principle of the multi-output Fibonacci type LFSR method, including the characteristics of the transformation matrix, the period of the output random numbers and the selection of the number of the stages. Then, we give the design procedure of how to design a multi-output Fibonacci type LFSR based uniform random number generator (URNG). Finally, we design a 16-output-of-23-stages LFSR based URNG which occupies only 36 slices and 23 flip flops and whose frequency is as high as 993MHz. Compared to multi LFSRs based URNG, our design saves more than 90% hardware devices. At last, we evaluate the quality of the generated random numbers with K-S method and get very good result.
