CAJ | 학술논문

运算放大器是模拟集成电路中用途最广、最基本的部件.随着系统功耗及电源电压的降低,传统的运算放大器已经不能满足低压下大共模输入范围及宽输出摆幅的要求.轨对轨运算放大器可以有效解决这一问题,然而传统的轨对轨运算放大器存在跨导不恒定的缺点.本文设计一种1.5V低功耗CMOS恒跨导轨对轨运算放大器,输入级采用最小电流选择电路,不仅实现了跨导的恒定,而且具有跨导不依赖于理想平方律模型、MOS管可以工作于所有区域、移植性好的优点.输出级采用前馈式AB类输出级,不仅能够精确控制输出晶体管电流,而且使输出达到轨对轨全摆幅.所设计的运算放大器采用了改进的级联结构,以减小运算放大器的噪声和失调.基于SMIC 0.18 μm工艺模型.利用Hspice软件对电路进行仿真,仿真结果表明,当电路驱动2 pF的电容负载以及10 KΩ的电阻负载时,直流增益达到83.2 dB,单位增益带宽为7.76 MHz,相位裕度为63°;输入输出均达到轨对轨全摆幅;在整个共模输入变化范围内跨导变化率仅为2.49%;具有较高的共模抑制比和电源抑制比;在1.5V低压下正常工作,静态功耗仅为0.24mW.
운산방대기시모의집성전로중용도최엄、최기본적부건.수착계통공모급전원전압적강저,전통적운산방대기이경불능만족저압하대공모수입범위급관수출파폭적요구.궤대궤운산방대기가이유효해결저일문제,연이전통적궤대궤운산방대기존재과도불항정적결점.본문설계일충1.5V저공모CMOS항과도궤대궤운산방대기,수입급채용최소전류선택전로,불부실현료과도적항정,이차구유과도불의뢰우이상평방률모형、MOS관가이공작우소유구역、이식성호적우점.수출급채용전궤식AB류수출급,불부능구정학공제수출정체관전류,이차사수출체도궤대궤전파폭.소설계적운산방대기채용료개진적급련결구,이감소운산방대기적조성화실조.기우SMIC 0.18 μm공예모형.이용Hspice연건대전로진행방진,방진결과표명,당전로구동2 pF적전용부재이급10 KΩ적전조부재시,직류증익체도83.2 dB,단위증익대관위7.76 MHz,상위유도위63°;수입수출균체도궤대궤전파폭;재정개공모수입변화범위내과도변화솔부위2.49%;구유교고적공모억제비화전원억제비;재1.5V저압하정상공작,정태공모부위0.24mW.
Operational amplifier is a basic device, most widely used in the analog integrated circuits. With the reduction of the system power consumption and with a low power supply voltage, the traditional operational amplifier can not meet the requirements of the large input common-mode range and the wide output swing under a low voltage. The rail-to-rail operational amplifier can meet these requirements. But the trans -conductance of the traditionalrail-to-rail operational amplifier is not constant. A 1.5 V low-power CMOS rail-to-rail operational amplifier is designed in this paper. A minimum current selection circuit is adopted in the input stage to achieve constant-g_m so that the trans-conductance is not independent of the ideal square law model, and the MOSFET transistors canwork not only in a strong inversion region but also in a weak inversion region. A feed-forward class AB output stage is used to ensure that the current of the output transistors to be controlled precisely and the output swing reaches rail to rail. In the operational amplifier, an improved compact circuit structure is adopted to reduce the noise and the offset of the operational amplifier. The circuit is simulated by using SMIC 0.18 μm process model and Hspice simulation software. The simulation results show that the DC gain is 83.2 dB, the unity gain bandwidth is 7.76 MHz, and the phase margin is 63°when the circuit is driving a load capacitance of 2pF and a load resistance of 10 kΩ. The input common-mode range and the output swing both reach rail to rail, and the variation of the gm is only 2.49%. The common-mode rejection ratio and the power supply rejection ratio of the circuit are both high. The circuit operates normally in a low voltage of 1.5 V, and the static power consumption is only 0.24 mW.