CAJ | 학술논문

引入了一种基于最新版本的IBIS模型给出的信息构造高速数字I／O缓冲器的瞬态行为模型的方法.阐述了从IBIS建模数据中得到这种瞬时状态转换行为模型的推导过程，同时获得了建模所需要的充分条件．与相应的晶体管级模型相比，该方法在获得了更高仿真精度的同时，提高了具有大量同步开关器件芯片互连的仿真速度．最后，为了验证模型的有效性，给出了该模型和晶体管级模型(SPICE模型)模拟结果的比较．
인입료일충기우최신판본적IBIS모형급출적신식구조고속수자I／O완충기적순태행위모 형적방법.천술료종IBIS건모수거중득도저충순시상태전환행위모형적추도과정，동시획득료건 모소수요적충분조건．여상응적정체관급모형상비，해방법재획득료경고방진정도적동시，제고료 구유대량동보개관기건심편호련적방진속도．최후，위료험증모형적유효성，급출료해모형화정체 관급모형(SPICE모형)모의결과적비교．
An approach for building a transient behavioral model of high-speed digital I/O buffers based on the information of the latest version IBIS model was introduced. The derivation procedures of such tran-sient state transition behavioral models from IBIS modeling data was mainly dealt with, and the sufficient condition for modeling was obtained. This scheme speeds up the simulations of chip interconnect with a large number of simultaneous switching devices, while acquiring better accuracy compared to the corre-sponding transistor level models. A comparison of simulation results between these models and transistor models (SPICE models) was made to verify the efficiency.