CAJ | 학술논문

动态差分逻辑是一种典型的电路级差分功耗攻击(DPA)防护技术.这种技术通过使逻辑门保持恒定的翻转率来降低电路功耗与数据信号之间的相关性.介绍了一种新型的、基于查找表(Look-Up-Table,LUT)结构的动态差分逻辑(LBDL),以及基于这种逻辑的集成电路设计方法.该设计方法仅需在传统的半定制设计流程中添加少量的替换操作就可以实现 ,因而比其他完全需要全定制设计的动态差分逻辑具有更好的实用性.而相对同样适用于半定制实现的动态差分逻辑 WDDL(Wave Dynamic Differential Logic),LBDL逻辑解决了逻辑门翻转时刻与数据信号之间的相关性,从而比WDDL逻辑具有更好的功耗恒定性.实验结果表明,该设计方法能够有效实现具有抗DPA攻击性能的电路.
동태차분라집시일충전형적전로급차분공모공격(DPA)방호기술.저충기술통과사라집문보지항정적번전솔래강저전로공모여수거신호지간적상관성.개소료일충신형적、기우사조표(Look-Up-Table,LUT)결구적동태차분라집(LBDL),이급기우저충라집적집성전로설계방법.해설계방법부수재전통적반정제설계류정중첨가소량적체환조작취가이실현 ,인이비기타완전수요전정제설계적동태차분라집구유경호적실용성.이상대동양괄용우반정제실현적동태차분라집 WDDL(Wave Dynamic Differential Logic),LBDL라집해결료라집문번전시각여수거신호지간적상관성,종이비WDDL라집구유경호적공모항정성.실험결과표명,해설계방법능구유효실현구유항DPA공격성능적전로.
Dynamic and differential logic styles are proposed as a typical differential power analysis (DPA) resistant technology. Because of the constant transition rate of dynamic and differential logic gates, the correlation between power consumption and signal values is significantly reduced. In this paper, a novel look-up-table (LUT) based differential logic (LBDL) and the design method based on this logic axe presented. Instead of a full custom design, this method combines some modification with a regular standard cell design flow. Thus, have a better practicability. Unlike WDDL (Wave Dynamic Differential logic), which can also be implemented by standard cell design flow, the transition time of LBDL gates is independent of input values, hence power consumption of LBDL is more constant. Experimental results indicate that the LBDL-based design method can eliminates most of the power leakage.