CAJ | 학술논문

乘加操作是数字信号处理器(DSP)的关键部分,单位时间内能够完成乘加操作的数量是衡量DSP芯片性能的一个重要指标.提出了一种应用于通用数字信号处理器的乘加器设计方法,在改进的Booth编码结合Wallace树压缩的基础上,通过在部分积压缩时插入MAC操作的加数,减少符号位扩展,实现了乘加操作的一步完成.提出一种有效的结构实现通用信号数字处理其所需的分数模式、零检测、饱和溢出控制、舍入操作等异常处理功能;并对乘加器的速度、面积、功耗等性能进行了分析.
승가조작시수자신호처리기(DSP)적관건부분,단위시간내능구완성승가조작적수량시형량DSP심편성능적일개중요지표.제출료일충응용우통용수자신호처리기적승가기설계방법,재개진적Booth편마결합Wallace수압축적기출상,통과재부분적압축시삽입MAC조작적가수,감소부호위확전,실현료승가조작적일보완성.제출일충유효적결구실현통용신호수자처리기소수적분수모식、령검측、포화일출공제、사입조작등이상처리공능;병대승가기적속도、면적、공모등성능진행료분석.
Multiplier-accumulator (MAC) is the key unit in digital signal processing (DSP). One of the most important parameters for DSP performance is the number of MAC operations in unit time. An efficient MAC design was proposed for general DSP application. Based on modified Booth encoding and Wallace tree merging, multiplying and accumulating operations were accomplished simultaneously by merging addend in the Wallace tree and reducing sign extension. An efficient structure was proposed to realize FRCT, zero-detection, overflow control, and rounding for general application DSP. Finally, analyses were made on the circuit for speed, size and power consumption reduction.