CAJ | 학술논문

设计了一种用于片上系统的无片外电容的CMOS低压差线性稳压器(LDO),其输出电压为3.3 V,最大输出电流为100 mA.该设计可以有效地减少芯片引脚和电路板面积.通过在传统结构上使用动态摆率增强电路和嵌套式米勒补偿技术,LDO在线性和负载响应过程中都有很强的稳定性.当输出电流从100 mA减小到1 mA时,过冲电压被限制在550 mV以内,稳定时间小于50μs.由于采用了30 nA的电流基准,本设计的静态功耗仅为3.3μA.通过CSMC公司0.5 μm CMOS工艺进行设计并流片验证,芯片测试结果与仿真结果吻合.
설계료일충용우편상계통적무편외전용적CMOS저압차선성은압기(LDO),기수출전압위3.3 V,최대수출전류위100 mA.해설계가이유효지감소심편인각화전로판면적.통과재전통결구상사용동태파솔증강전로화감투식미륵보상기술,LDO재선성화부재향응과정중도유흔강적은정성.당수출전류종100 mA감소도1 mA시,과충전압피한제재550 mV이내,은정시간소우50μs.유우채용료30 nA적전류기준,본설계적정태공모부위3.3μA.통과CSMC공사0.5 μm CMOS공예진행설계병류편험증,심편측시결과여방진결과문합.
A CMOS (complementary metal-oxide-semiconductor transistor)low-dropout regulator(LDO) with 3.3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented.By utilizing a dynamic slew-rate enhancement(SRE) circuit and nested Miller compensation(NMC)on the LDO structure,the proposed LDO provides high stability during line and load regulatiOn without off-chip load capacitors.The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA.By using a 30 nA reference current,the quiescent current is 3.3μA.The proposed design is implemented by CSMC 0.5 tun mixed-signal process.The experimental results agree with the simulation results.