半导体学报
半導體學報
반도체학보
CHINESE JOURNAL OF SEMICONDUCTORS
2008年
3期
423-427
,共5页
纳米CMOS%互连耦合串扰%分布式RLC解析模型%参数提取%函数逼近
納米CMOS%互連耦閤串擾%分佈式RLC解析模型%參數提取%函數逼近
납미CMOS%호련우합천우%분포식RLC해석모형%삼수제취%함수핍근
nanometer CMOS%interconnect coupling crosstalk%parallel RLC analytical model%parameter extraction%function approximation
基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.
基于65nm CMOS工藝,綜閤攷慮電容耦閤與電感耦閤效應,提齣瞭一種互連線耦閤串擾分佈式RLC解析模型.採用函數逼近理論與降階技術,在斜階躍輸入信號下,提齣瞭被榦擾線遠耑的串擾數值錶達式.基于65nm CMOS工藝,對不同的互連耦閤呎吋下的分佈式RLC串擾解析模型和Hspice倣真結果進行瞭比較,誤差絕對值都在2.50%內,能應用于納米級SOC的計算機輔助設計.
기우65nm CMOS공예,종합고필전용우합여전감우합효응,제출료일충호련선우합천우분포식RLC해석모형.채용함수핍근이론여강계기술,재사계약수입신호하,제출료피간우선원단적천우수치표체식.기우65nm CMOS공예,대불동적호련우합척촌하적분포식RLC천우해석모형화Hspice방진결과진행료비교,오차절대치도재2.50%내,능응용우납미급SOC적계산궤보조설계.
Based on the 65nm CMOS process, a novel parallel RLC coupling interconnect analytical model is presented syn- thetically considering parasitical capacitive and parasitical inductive effects. Applying function approximation and model order-reduction to the model,we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition. For various interconnect coupling sizes, the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2. 50% error compared with Hspice simulation in a 65nm CMOS process. This model can be used in computer-aided-design of nanometer SOCs.
