CAJ | 학술논문

RSA非对称密钥算法因其算法的复杂性,硬件实现开销一直较大.针对该问题,提出采用256位数据宽度处理的方式代替传统的1024位数据宽度处理,通过折叠数据通道,精简电路结构,并使用片内静态随机存储器(SRAM)减小实现面积,实现了应用于资源受限环境下的小面积RSA硬件加密引擎.采用华虹NEC0.25μm工艺实现该电路,整个设计规模约为24k等效门,最大工作频率为100MHz,相比于实用芯片西门子SLE66CX160S,本实现的面积缩小了55.63%.
RSA비대칭밀약산법인기산법적복잡성,경건실현개소일직교대.침대해문제,제출채용256위수거관도처리적방식대체전통적1024위수거관도처리,통과절첩수거통도,정간전로결구,병사용편내정태수궤존저기(SRAM)감소실현면적,실현료응용우자원수한배경하적소면적RSA경건가밀인경.채용화홍NEC0.25μm공예실현해전로,정개설계규모약위24k등효문,최대공작빈솔위100MHz,상비우실용심편서문자SLE66CX160S,본실현적면적축소료55.63%.
Due to the complexity of the popular asymmetric-key encryption algorithm RSA, the hardware implemen-tation has a too large overhead to be used in resource-constrained systems. In order to solve this problem, an RSA encryption engine based on 256 bit data width processor is designed, which greatly reduces the area required by RSA. Synthesis results show that, in addition to the basic function implementation, the improved RSA design reduces the area by 55.63% with respect to SLE66CX160S of Siemens. It has 24 k gates count with a maximum clock frequency of 100 MHz. The implemented RSA engine meets the design requirements.