CAJ | 학술논문

结合电荷放大原理,通过设计高性能的运算放大器, 较好地完成了杂散电容的屏蔽,实现了高可靠性的微电容检测.采用CSMC 0.5 μm CMOS工艺,用Cadence Spectre对其进行仿真验证,能精确检测出aF量级的微电容.结合考虑不可避免的工艺误差,对差分标称电容的失配进行分析与校准.结果表明: 失配仅带来固定的失调,不会对C/V电路的灵敏度造成显著的影响.
결합전하방대원리,통과설계고성능적운산방대기, 교호지완성료잡산전용적병폐,실현료고가고성적미전용검측.채용CSMC 0.5 μm CMOS공예,용Cadence Spectre대기진행방진험증,능정학검측출aF량급적미전용.결합고필불가피면적공예오차,대차분표칭전용적실배진행분석여교준.결과표명: 실배부대래고정적실조,불회대C/V전로적령민도조성현저적영향.
Based on the principle of charge amplifier, a high performance operational amplifier was designed to shield stray capacitance, which enables high reliability small capacitance measurement.Fabricated in CSMC's 0.5 μm CMOS process and simulated with Cadence Spectre, the circuit can measure small capacitance precisely with a resolution of aF.Finally, mismatch of differential nominal capacitance caused by inevitable manufacturing errors was analyzed and calibrated.Results showed that mismatch only led to fixed drift, but no significant effect on sensitivity of the C/V circuit.