清华大学学报(英文版)
清華大學學報(英文版)
청화대학학보(영문판)
TSINGHUA SCIENCE AND TECHNOLOGY
2001年
4期
361-368
,共8页
张武健%邱晓海%周润德%陈弘毅%Kondo Toshio%Nakashima Takayoshi%Ishitani Tsunehachi
張武健%邱曉海%週潤德%陳弘毅%Kondo Toshio%Nakashima Takayoshi%Ishitani Tsunehachi
장무건%구효해%주윤덕%진홍의%Kondo Toshio%Nakashima Takayoshi%Ishitani Tsunehachi
This paper describes an efficient, low-latency systolic array architecture for full searches inblock-matching motion estimation. Conventional one-dimensional systolic array architecture is used to developa novel ring-like systolic array architecture through operator rescheduling considering the symmetry of the dataflow. High-latency delay due to stuffing of the array pipeline in the conventional architecture was eliminated.The new architecture delivers a higher throughput rate, achieves higher processor utilization, and haslow-power consumption. In addition, the minimum memory bandwidth of the conventional architecture ispreserved.``
