CAJ | 학술논문

设计了一个工作在3.0V的10位40MHz流水线A/D转换器,采用了时分复用运算放大器,低功耗的增益自举telescopic运放,低功耗动态比较器,器件尺寸逐级减小优化功耗.在40MHz的采样时钟,0.5MHz的输入信号的情况下测试,可获得8.1位有效精度,最大积分非线性为2.2LSB,最大微分非线性为0.85LSB,电路用0.25μm CMOS工艺实现,面积为1.24mm2,功耗仅为59mW,其中同时包括为A/D转换器提供基准电压和电流的一个带隙基准源和缓冲电路.
설계료일개공작재3.0V적10위40MHz류수선A/D전환기,채용료시분복용운산방대기,저공모적증익자거telescopic운방,저공모동태비교기,기건척촌축급감소우화공모.재40MHz적채양시종,0.5MHz적수입신호적정황하측시,가획득8.1위유효정도,최대적분비선성위2.2LSB,최대미분비선성위0.85LSB,전로용0.25μm CMOS공예실현,면적위1.24mm2,공모부위59mW,기중동시포괄위A/D전환기제공기준전압화전류적일개대극기준원화완충전로.
This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter (ADC) fabricated in a 0. 25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques:a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits, a maximum differential nonlinearity of a 0. 85 least significant bit (LSB), and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.