高速FFT的蝶形单元和地址生成器优化
고속FFT적접형단원화지지생성기우화
High speed FFT butterfly unit and addresses generator optimization
  • 万方数据
    计算机工程与应用 계산궤공정여응용
    COMPUTER ENGINEERING AND APPLICATIONS
    2010年 8期 64-66,70 ,共4页

    王镇道%王宇峰%陈迪平

    왕진도%왕우봉%진적평

    快速傅里叶变换%Wallace树%地址生成器%蝶形单元 快速傅裏葉變換%Wallace樹%地阯生成器%蝶形單元
    쾌속부리협변환%Wallace수%지지생성기%접형단원
    Fast Fourier Transform(FFT)%Wallace tree%addresses generator%butterfly unit
    提出了FFT处理器的堞形单元和地址发生器优化方案.通过改进Wallace树型加法器阵列结构,提高了蝶形单元乘法器的工作频率.提出了地址快速生成算法,该算法在快速产生地址的同时降低了读取旋转因子ROM的功耗.在Xilinx的Vertex-Ⅱ系列FPGA上实现,该处理器可以稳定工作在150 MHz时钟下,速度满足设计指标.
    제출료FFT처리기적첩형단원화지지발생기우화방안.통과개진Wallace수형가법기진렬결구,제고료접형단원승법기적공작빈솔.제출료지지쾌속생성산법,해산법재쾌속산생지지적동시강저료독취선전인자ROM적공모.재Xilinx적Vertex-Ⅱ계렬FPGA상실현,해처리기가이은정공작재150 MHz시종하,속도만족설계지표.
    An optimized method of butterfly unit and addresses generator is proposed.By improving the Wallace tree adder array structure,the frequency of butterfly unit multiplier is improved.The rapid algorithm of addresses generation is proposed,with this algorithm,the addresses can be generated quickly,and the power of reading twiddles ROM is decreased.With Vertex-Ⅱ series FPGA of Xilinx,the design is implemented,the system can operate stably at 150 MHz,the speed meets the requirements.
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