CAJ | 학술논문

Usually a single MPEG2 video encoder chip realizes the multiple post-stage tasks of motionestimation, such as motion vector refinement and prediction error generation, using multiple hardwaremodules. This paper proposes a new architecture using only a single module to implement the post-stage tasksof motion estimation, which has a single instruction stream over multiple data streams (SIMD). The newarchitecture is simple and more regular; capable of providing sufficient computational power and of adapting tothe encoding flexibility required by the MPEG2 standard. Therefore, it is a more suitable architecture for thesystem on a chip. NEL Corporation (NTT Electronics, Japan) has integrated a circuit based on this architectureinto the single MPEG2 MP·ML encoder chip, which uses the multiresolution telescopic search motionestimation algorithm. Using 0. 25μm CMOS, four-metal layer technology, this circuit has 15.4 M gates with anarea of about 29 mm2. The operating clock frequency is 81 MHz.``