半导体技术
半導體技術
반도체기술
SEMICONDUCTOR TECHNOLOGY
2010年
2期
162-165
,共4页
芯片埋置技术%聚合物内埋置芯片%等效应力%疲劳寿命
芯片埋置技術%聚閤物內埋置芯片%等效應力%疲勞壽命
심편매치기술%취합물내매치심편%등효응력%피로수명
embedded chip technology%embedded chip in polymer%equivalent stress%fatigue life
芯片埋置技术可以提高电子组装密度以及电子产品的可靠性,是微电子封装发展的趋势.建立了聚合物内埋置芯片(CiP)的有限元模型,分析了器件的最大等效应力、剥离应力以及总等效塑性应变,得到该结构容易失效的关键位置.采用修正Coffin-Manson公式对Cu引线的疲劳寿命进行了预测,并分析了Cu引线厚度对其寿命的影响.结果表明,Cu微孔与焊盘交界处的等效应力、剥离应力以及等效塑性应变较大,容易引起裂纹或分层;Cu引线的厚度对疲劳失效起着至关重要的作用,增加Cu引线厚度可以大幅度提高Cu引线的疲劳寿命.
芯片埋置技術可以提高電子組裝密度以及電子產品的可靠性,是微電子封裝髮展的趨勢.建立瞭聚閤物內埋置芯片(CiP)的有限元模型,分析瞭器件的最大等效應力、剝離應力以及總等效塑性應變,得到該結構容易失效的關鍵位置.採用脩正Coffin-Manson公式對Cu引線的疲勞壽命進行瞭預測,併分析瞭Cu引線厚度對其壽命的影響.結果錶明,Cu微孔與銲盤交界處的等效應力、剝離應力以及等效塑性應變較大,容易引起裂紋或分層;Cu引線的厚度對疲勞失效起著至關重要的作用,增加Cu引線厚度可以大幅度提高Cu引線的疲勞壽命.
심편매치기술가이제고전자조장밀도이급전자산품적가고성,시미전자봉장발전적추세.건립료취합물내매치심편(CiP)적유한원모형,분석료기건적최대등효응력、박리응력이급총등효소성응변,득도해결구용역실효적관건위치.채용수정Coffin-Manson공식대Cu인선적피로수명진행료예측,병분석료Cu인선후도대기수명적영향.결과표명,Cu미공여한반교계처적등효응력、박리응력이급등효소성응변교대,용역인기렬문혹분층;Cu인선적후도대피로실효기착지관중요적작용,증가Cu인선후도가이대폭도제고Cu인선적피로수명.
Embedded chip technology can enhance the density of electronic assembly as well as the reliability of electronic products, and it becomes the development trend of microelectronic packaging. The finite element model of embedded chip in polymer (CiP) was built and the maximum equivalent stress, peel stress and equivalent plastic strain were analyzed. The key position of structure failure was obtained. The modified Coffin-Manson formula was employed to predict the fatigue life and the impact of copper line thickness on the fatigue life was surveyed. The results show that the maximum equivalent stress, peel stress and equivalent plastic strain easily lead to crack or delamination, which always appear at the interface of copper vias and pads. The thickness of copper line plays an important role in fatigue failure and increasing the thickness of the copper line will enhance the fatigue life significantly.