CAJ | 학술논문

采用FPGA作为数字信号发生器,利用线性移位寄存器产生要求的M序列,作为数字信号以及模拟信道噪声信号。利用单片机（MSP430FG4618）产生不同的频率,控制M序列时钟,从而改变数据率。采用集成滤波器芯片LT1568,通过改变外围电阻,实现不同的截止频率,模拟信道幅频特性。信号分析电路采用低通滤波器降低信号噪声。同步时钟可用时,将滤波调理之后的数字信号接入示波器,同时利用同步时钟产生同步扫描信号,作为示波器外触发信号,即可稳定显示数字信号眼图。同步时钟不可用时,先进行同步时钟提取,而后产生同步扫描信号,触发显示眼图。
채용FPGA작위수자신호발생기,이용선성이위기존기산생요구적M서렬,작위수자신호이급모의신도조성신호。이용단편궤（MSP430FG4618）산생불동적빈솔,공제M서렬시종,종이개변수거솔。채용집성려파기심편LT1568,통과개변외위전조,실현불동적절지빈솔,모의신도폭빈특성。신호분석전로채용저통려파기강저신호조성。동보시종가용시,장려파조리지후적수자신호접입시파기,동시이용동보시종산생동보소묘신호,작위시파기외촉발신호,즉가은정현시수자신호안도。동보시종불가용시,선진행동보시종제취,이후산생동보소묘신호,촉발현시안도。
The system uses the FPGA as digital signal generator,in which a linear shift register generates the M sequence,as the digital signal to be transmitted and simulated channel noise.Using SCM（MSP430FG4618）,this paper gets different frequency signals to control the clock of the M sequence,thus changing the data rate.Integrated filter chip,LT1568,simply by changing its external resistor to get different cut-off frequencies,is used to shape channel amplitude-frequency characteristics and a low pass filter is used to reduce signal noise.When synchronous clock is available,it can be used directly as synchronous scanning signal connected to the external trigger of oscilloscope.Meanwhile,the digital signal after filtering is connected to oscilloscope and steady eye patterns can be observed.When synchronized clock is not available,we extract synchronized clock form the transmitted digital signal firstly,and then generate synchronous scanning signal that triggers display of eye patterns.