CAJ | 학술논문

提出了一种新型的具有简易APFC的单片SPIC电路.通过采用集成在SPIC内部的延迟电路,使有APFC电路的总线电压由600V下降为400V.在电路中,采用长沟道的NMOS管来代替大电阻以节省版图面积.在保证所需的功率因数的情况下,总线电压的下降可以直接导致功率开关器件的比导通电阻下降,减小功率器件的损耗,提高电路的效率.同时,总线电压下降,也使电路成本降低.此外,还同时设计了相应的高压过压保护电路.理论分析与模拟结果都证明该设计是正确的和有效的.
제출료일충신형적구유간역APFC적단편SPIC전로.통과채용집성재SPIC내부적연지전로,사유APFC전로적총선전압유600V하강위400V.재전로중,채용장구도적NMOS관래대체대전조이절성판도면적.재보증소수적공솔인수적정황하,총선전압적하강가이직접도치공솔개관기건적비도통전조하강,감소공솔기건적손모,제고전로적효솔.동시,총선전압하강,야사전로성본강저.차외,환동시설계료상응적고압과압보호전로.이론분석여모의결과도증명해설계시정학적화유효적.
A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The Vbus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.The lower Vbus results in a smaller Ron(on-resistance) of power switcher,which reduces the power loss of the power devices,improves the efficiency of the circuit,and reduces the cost of circuits.An integrated high voltage over voltage protect circuit is also designed in the circuits.Theory and simulations both prove the correctness and availability of the design.