浙江大学学报(英文版)
浙江大學學報(英文版)
절강대학학보(영문판)
JOURNAL OF ZHEJIANG UNIVERSITY SCIENCE
2004年
9期
1102-1105
,共4页
System-On-Chip%Verilog%HDL%Verification%Reuse
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
