CAJ | 학술논문

为了使一个10 Gbit/s 2∶1半速率复接器电路能够在无外部提供时钟的环境中工作,需要一个5 Gbit/s时钟恢复电路从一路输入数据中提取出所需时钟.该时钟恢复电路采用3级环形压控振荡器,以克服2级振荡器存在的起振不可靠和4级振荡器振荡频率低的问题；采用鉴频鉴相器来增加牵引范围,以适应由于工艺、电压及温度偏差等原因而导致的压控振荡器的宽调谐范围；采用SMIC 0.18-μm CMOS工艺,核心电路面积为170 μm×270μm.测试表明:在1.8 V电压下,该电路功耗大约为90 mW,输入灵敏度低于25 mV,输出摆幅大于300mV,且具有-114 dBc/Hz@1 MHz的相位噪声和1 GHz牵引范围.
위료사일개10 Gbit/s 2∶1반속솔복접기전로능구재무외부제공시종적배경중공작,수요일개5 Gbit/s시종회복전로종일로수입수거중제취출소수시종.해시종회복전로채용3급배형압공진탕기,이극복2급진탕기존재적기진불가고화4급진탕기진탕빈솔저적문제；채용감빈감상기래증가견인범위,이괄응유우공예、전압급온도편차등원인이도치적압공진탕기적관조해범위；채용SMIC 0.18-μm CMOS공예,핵심전로면적위170 μm×270μm.측시표명:재1.8 V전압하,해전로공모대약위90 mW,수입령민도저우25 mV,수출파폭대우300mV,차구유-114 dBc/Hz@1 MHz적상위조성화1 GHz견인범위.
In order to make a 10 Gbit/s 2:1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery (CR) circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator (VCO) is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO.A phase frequency detector (PFD) is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature (PVT) variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm × 270μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.