CAJ | 학술논문

提出了一种适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管.报道了圆柱体全包围栅场效应管器件物理分析、技术仿真结果以及器件制作详细工艺流程.与其他常规鳍形场效应管器件(FinFET)相比,该器件特别适用于解决常规鳍形场效应管器件所面临的问题,进一步提高器件性能及按比例缩小能力.技术仿真结果显示,圆柱体全包围栅场效应管具备许多常规鳍形场效应管器件,其中包括长方体全包围栅场效应管所不具备的优点.就圆柱体全包围栅场效应管器件结构而言,该器件由无数多个将圆柱体形沟道全部包围的栅所控制.由于克服了由不对称场的积聚,如锐角效应所导致的漏电,器件沟道的电完整性得到很大改善.详细讨论了器件制作工艺流程,提出的工艺流程简单并且与常规CMOS工艺流程兼容.
제출료일충괄용우안비례축소지아10nm적원주체전포위책장효응관.보도료원주체전포위책장효응관기건물리분석、기술방진결과이급기건제작상세공예류정.여기타상규기형장효응관기건(FinFET)상비,해기건특별괄용우해결상규기형장효응관기건소면림적문제,진일보제고기건성능급안비례축소능력.기술방진결과현시,원주체전포위책장효응관구비허다상규기형장효응관기건,기중포괄장방체전포위책장효응관소불구비적우점.취원주체전포위책장효응관기건결구이언,해기건유무수다개장원주체형구도전부포위적책소공제.유우극복료유불대칭장적적취,여예각효응소도치적루전,기건구도적전완정성득도흔대개선.상세토론료기건제작공예류정,제출적공예류정간단병차여상규CMOS공예류정겸용.
A gate-all-around cylindrical (GAAC) transistor for sub-10nm scaling is proposed. The GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure are reported for the first time. Among all other novel Fin- FET devices,the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conven- tional multi-gate FinFET and improving the device performance and the scale down capability. According to our simula-tion,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate.all-around rectangular (GAAR) devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen-tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is character-ized by its simplicity and full compatibility with conventional planar CMOS technology.