电子学报
電子學報
전자학보
ACTA ELECTRONICA SINICA
2010年
2期
352-358
,共7页
同时多线程%超长指令字%数字信号处理器
同時多線程%超長指令字%數字信號處理器
동시다선정%초장지령자%수자신호처리기
simultaneous multithreading%VLIW architecture%digital signal processor
本文提出了一种支持同时多线程的动态分发超长指令字(VLIW)数字信号处理器(DSP)架构.该DSP架构上可以同时运行多个线程,功能单元可以执行来自多个线程的指令,有效地提高DSP的指令吞吐率.为了使多个线程的指令更有效地调度分发到功能单元,该DSP架构还支持指令动态分发,由硬件分发单元而不是编译器来完成多线程指令的动态分配.实验结果表明,相比于单线程而言,本文提出的VLIW DSP架构可以提高功能单元利用率,隐藏存储器访问时延,使处理器的指令吞吐率平均提高约26.89%.
本文提齣瞭一種支持同時多線程的動態分髮超長指令字(VLIW)數字信號處理器(DSP)架構.該DSP架構上可以同時運行多箇線程,功能單元可以執行來自多箇線程的指令,有效地提高DSP的指令吞吐率.為瞭使多箇線程的指令更有效地調度分髮到功能單元,該DSP架構還支持指令動態分髮,由硬件分髮單元而不是編譯器來完成多線程指令的動態分配.實驗結果錶明,相比于單線程而言,本文提齣的VLIW DSP架構可以提高功能單元利用率,隱藏存儲器訪問時延,使處理器的指令吞吐率平均提高約26.89%.
본문제출료일충지지동시다선정적동태분발초장지령자(VLIW)수자신호처리기(DSP)가구.해DSP가구상가이동시운행다개선정,공능단원가이집행래자다개선정적지령,유효지제고DSP적지령탄토솔.위료사다개선정적지령경유효지조도분발도공능단원,해DSP가구환지지지령동태분발,유경건분발단원이불시편역기래완성다선정지령적동태분배.실험결과표명,상비우단선정이언,본문제출적VLIW DSP가구가이제고공능단원이용솔,은장존저기방문시연,사처리기적지령탄토솔평균제고약26.89%.
A novel simultaneous multithreading (SMT) VLIW DSP architecture with dynamic dispatch mechanism was pre-sented. The SMT technology exploits the unused instruction slots by converting the thread-level parallelism to the instruclion-level parallelism,improving the efficiency. With the dynamic dispatch mechanism, the processor issues instructions to functional unit at run-time rather than at compile-time, such that the issue conflicts among multiple threads are reduced significantly.The results show that the DSP architecture can effectively increase the functional unit utilization, hide the memory access latency, such that the yo-cessor throughput is improved by 26.89% with respect to single thread architecture .
