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2012年
2期
47-49
,共3页
H.264%DCT%FPGA%整数变换
H.264%DCT%FPGA%整數變換
H.264%DCT%FPGA%정수변환
H.264%DCT（Discrete Cosine Transform）%FPGA（Field-Programmable Gate Array）%integer transform
该文在分析了H.264整数DCT（Discrete Cosine Transform）变换原理的基础上,介绍了一种实现4×4前向整数变换的新算法。该算法较多地运用了矩阵运算,与传统的将一个二维DCT变换转变为两个一维DCT变换相比,省略了转置模块,降低了时钟延时,减少了资源占用,更利于达到基于H.264的视频信号处理的性能要求。根据新的算法编写了verilog程序并在QuartusⅡ8.0软件中进行了仿真并得出结果。
該文在分析瞭H.264整數DCT（Discrete Cosine Transform）變換原理的基礎上,介紹瞭一種實現4×4前嚮整數變換的新算法。該算法較多地運用瞭矩陣運算,與傳統的將一箇二維DCT變換轉變為兩箇一維DCT變換相比,省略瞭轉置模塊,降低瞭時鐘延時,減少瞭資源佔用,更利于達到基于H.264的視頻信號處理的性能要求。根據新的算法編寫瞭verilog程序併在QuartusⅡ8.0軟件中進行瞭倣真併得齣結果。
해문재분석료H.264정수DCT（Discrete Cosine Transform）변환원리적기출상,개소료일충실현4×4전향정수변환적신산법。해산법교다지운용료구진운산,여전통적장일개이유DCT변환전변위량개일유DCT변환상비,성략료전치모괴,강저료시종연시,감소료자원점용,경리우체도기우H.264적시빈신호처리적성능요구。근거신적산법편사료verilog정서병재QuartusⅡ8.0연건중진행료방진병득출결과。
In this paper,the principle of the integer DCT in H.264 is analyzed and then a new algorithm for realization of 4×4 forward integer transform is introduced.There is much a lot of operation of matrix in this algorithm.Compared with the traditional method of decomposing a 2-dimentional DCT transform into two 1-dimentional DCT transforms,the new one doesn＇t need transpose module,makes the clock cycle delay lower and uses less resources in FPGA,which is more suitable for video signal processing based on H.264.According to the new algorithm,the Verilog program is written and run in QuartusⅡ8.0.
