CAJ | 학술논문

针对自举开关中的寄生效应和导通电阻的非线性问题提出了一种新的低压低电阻的自举开关.同时利用增益增强技术设计高直流增益和高单位增益带宽的运放,从而保证采样保持电路和子级电路的性能.基于以上技术,设计了一个10位100Ms/s流水线模数转换器,该模数转换器用0.18μm CMOS工艺流片验证.经测试,该模数转换器可以在采样率为100MHz,输入频率分别为在6.26和48.96MHz的情况下分别获得54.2和49.8dB的信噪比.
침대자거개관중적기생효응화도통전조적비선성문제제출료일충신적저압저전조적자거개관.동시이용증익증강기술설계고직류증익화고단위증익대관적운방,종이보증채양보지전로화자급전로적성능.기우이상기술,설계료일개10위100Ms/s류수선모수전환기,해모수전환기용0.18μm CMOS공예류편험증.경측시,해모수전환기가이재채양솔위100MHz,수입빈솔분별위재6.26화48.96MHz적정황하분별획득54.2화49.8dB적신조비.
A novel low-voltage,low constant-impedance switch is proposed,which not only eliminates the parasitic capaci-tor but also reduces the variation of switch "on" resistance. With the gain-boost technology, the operational transconduct-ance amplifier used in this analog-to-digital converter (ADC) achieves enough DC gain and unity-gain frequency under thelow voltage supply and to guarantee the performance of the sample and hold circuit (S/H) and the sub-stages. Based onthese methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltagesupply. The ADC achieves an SNR of 54. 2dB (input frequency of 6.26MHz) and an SNR of 49.8dB (input frequency of48. 96MHz) when the sampling frequency is 100MHz.