固体电子学研究与进展
固體電子學研究與進展
고체전자학연구여진전
RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS
2010年
1期
119-123
,共5页
低电压差分信号传输%高速接口%发送器%接收器
低電壓差分信號傳輸%高速接口%髮送器%接收器
저전압차분신호전수%고속접구%발송기%접수기
LVDS%high speed interface%transmitter%receiver
设计了一个采用0.18 μm 1.8 V/3.3 V CMOS工艺制造的千兆比特数据率LVDS I/O 接口电路.发送器电路采用内部参考电流源和片上匹配电阻,使工艺偏差、温度变化对输出信号幅度的影响减小50%;接收器电路采用一种改进的结构,通过检测输入共模电平,自适应调整预放大器偏置电压,保证跨导Gm在LVDS标准[1]要求的共模范围内恒定,因此芯片在接收端引入的抖动最小.芯片面积0.175 mm~2,3.3 V电源电压下功耗为33 mW,测试表明此接口传输速率达到1 Gb/s.
設計瞭一箇採用0.18 μm 1.8 V/3.3 V CMOS工藝製造的韆兆比特數據率LVDS I/O 接口電路.髮送器電路採用內部參攷電流源和片上匹配電阻,使工藝偏差、溫度變化對輸齣信號幅度的影響減小50%;接收器電路採用一種改進的結構,通過檢測輸入共模電平,自適應調整預放大器偏置電壓,保證跨導Gm在LVDS標準[1]要求的共模範圍內恆定,因此芯片在接收耑引入的抖動最小.芯片麵積0.175 mm~2,3.3 V電源電壓下功耗為33 mW,測試錶明此接口傳輸速率達到1 Gb/s.
설계료일개채용0.18 μm 1.8 V/3.3 V CMOS공예제조적천조비특수거솔LVDS I/O 접구전로.발송기전로채용내부삼고전류원화편상필배전조,사공예편차、온도변화대수출신호폭도적영향감소50%;접수기전로채용일충개진적결구,통과검측수입공모전평,자괄응조정예방대기편치전압,보증과도Gm재LVDS표준[1]요구적공모범위내항정,인차심편재접수단인입적두동최소.심편면적0.175 mm~2,3.3 V전원전압하공모위33 mW,측시표명차접구전수속솔체도1 Gb/s.
This paper presents the design and the implementation of 1 Gb/s LVDS I/O interface in standard CMOS technology. By using an internal temperature independent current source and an integrated terminal resistor, the variation of LVDS signal amplitude caused by process deviation and temperature variation can be reduced 50%. The preamplifier of the receiver implements folded-cascode architecture, accompaned with an input common mode voltage detecting circuit. Thus, the input common mode voltage measurement range can satisfy the LVDS std.[1] without using low threshold transistors. And the gain of the preamplifier keeps constant independent of the common mode voltage variations, which minimized the introduced jitter when the proposed transceiver works as a buffer. The test chip occupies 0.175 mm~2 and exhibits a power consumption of 33 mW with 3.3 V supply voltage. Test indicates that the transceiver can operate up to 1 Gb/s.
