CAJ | 학술논문

对一种CMOS/SOI 64Kb静态随机存储器进行了研究，其电路采用8K×8的并行结构体系．为了提高电路的速度，采用地址转换监控(Address-Translate-Detector，ATD)、两级字线(Double-Word-Line，DWL)和新型的两级灵敏放大等技术，电路存取时间仅40ns；同时，重点研究了SOI静电泄放(Electrostatic-Discharge，ESD)保护电路和一种改进的灵敏放大器，设计出一套全新ESD电路，其抗静电能力高达4200—4500V．SOI 64Kb CMOS静态存储器采用1.2μm SOI CMOS抗辐照工艺技术，芯片尺寸为7.8mm×7.24mm．
대일충CMOS/SOI 64Kb정태수궤존저기진행료연구，기전로채용8K×8적병행결구체계．위료제고전로적속도，채용지지전환감공(Address-Translate-Detector，ATD)、량급자선(Double-Word-Line，DWL)화신형적량급령민방대등기술，전로존취시간부40ns；동시，중점연구료SOI정전설방(Electrostatic-Discharge，ESD)보호전로화일충개진적령민방대기，설계출일투전신ESD전로，기항정전능력고체4200—4500V．SOI 64Kb CMOS정태존저기채용1.2μm SOI CMOS항복조공예기술，심편척촌위7.8mm×7.24mm．
An SOI SRAM with 8K×8 concurrent system has been described.To reduce the power and raise the speed of circuit,addess-transition-detection,doubl-word-line and double double-stage sense amplifier technology,etc.are adopted.Fast access time of 40ns is abtained. Placing great emphasis on the investigation of SOI ESD (Electrostatic-Discharge) protection circuit and the improved amplifier,a set of optimum ESD circuit is designed,which is capable of protecting from the static discharge in excess of 4200—4500V.1.2μm SOI CMOS technology has been developed for SOI 64Kb CMOS SRAM,with the chip size of 7.8mm×7.24mm.