CAJ | 학술논문

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm 3.3V标准数字工艺实现.
개소료일개채용절첩내삽결구적CMOS모수전환기,괄합우감입식응용.해전로여표준적수자공예완전겸용,경과개진적무수전조취능실현적절첩모괴유조우감소심편면적.재수입급,실조평균기술강저료수입전용,이분포식채양보지전로적운용칙제고료신호여조성적실진비.해200MHz채양빈솔8위절첩내삽결구적CMOS모수전환기재3.3V전원전압하,총공모위177mW,용0.18μm 3.3V표준수자공예실현.
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.