CAJ | 학술논문

CMOS工艺的发展要求栅介质层厚度不断减薄,随着栅极漏电流的不断增大使用准静态的方法测量器件特性不稳定.根据这一情况,提出用高频电容电压(C-V)来评价深亚微米和超深亚微米器件工艺.通过高频C-V法结合MOS相关理论可以得到介质层的厚度、最大耗尽层宽度、阈值电压、平带电压等参数以及栅介质层中各种电荷密度的分布,用以评价栅介质层和衬底的界面特性.文章提出通过电导对测量结果进行修正,使其能够适用更小尺寸器件的要求,使高频C-V法能够在不同的工艺下得到广泛的应用.
CMOS공예적발전요구책개질층후도불단감박,수착책겁루전류적불단증대사용준정태적방법측량기건특성불은정.근거저일정황,제출용고빈전용전압(C-V)래평개심아미미화초심아미미기건공예.통과고빈C-V법결합MOS상관이론가이득도개질층적후도、최대모진층관도、역치전압、평대전압등삼수이급책개질층중각충전하밀도적분포,용이평개책개질층화츤저적계면특성.문장제출통과전도대측량결과진행수정,사기능구괄용경소척촌기건적요구,사고빈C-V법능구재불동적공예하득도엄범적응용.
The thickness of gate oxide have been scaled down aggressively with the development of the CMOS technologies. However, the leakage current has increased drastically which made the measurement of quasi-static is instability. The processes of deep-submicron and uhra-deep-submicron devices were controlled and evaluated by high frequency capacitor-voltage (C-V) method. By this way, according the MOS theory we can extract the parameters of the MOS devices including the thickness of the dielectric, the maximal width of the depletion layer, threshold voltage, fiat voltage, and the distribution of the charges in dielectric, which is used to evaluate the characterization of the interface state between substrate and dielectric. A method can correct the measurement result by conductance has been proposed in this paper to made the mehod of high frequency C-V can used in smaller dimension devices. This can enable the high frequency C-V meathod to use in more widely.