前向MLP网络的FPGA实现
전향MLP망락적FPGA실현
FPGA Implementation of Feed-Forward MLP Neural Networks
  • 万方数据
    数据采集与处理 수거채집여처리
    JOURNAL OF DATA ACQUISITION & PROCESSING
    2010年 1期 39-43 ,共5页

    都军伟%王永纲%杨阳%李凯

    도군위%왕영강%양양%리개

    多层感知器%FPGA%CORDIC算法%分布式算法 多層感知器%FPGA%CORDIC算法%分佈式算法
    다층감지기%FPGA%CORDIC산법%분포식산법
    multi-layer perceptron%FPGA%CORDIC algorithm%distributed algorithm
    分别采用CORDIC(Coordinate rotation digital computer)算法和分布式算法实现多层感知器网络的传输函数计算和输入与权重乘积和计算,通过模块复用的方法构造了一个用于函数逼近的、无需乘法器的神经网络,并在NoisⅡ开发平台上测试了该网络的性能.该网络每17个时钟周期输出一个数据,占用FPGA的7781个LE(Logic element)和8976 bit存储器,具有良好的扩展性.
    분별채용CORDIC(Coordinate rotation digital computer)산법화분포식산법실현다층감지기망락적전수함수계산화수입여권중승적화계산,통과모괴복용적방법구조료일개용우함수핍근적、무수승법기적신경망락,병재NoisⅡ개발평태상측시료해망락적성능.해망락매17개시종주기수출일개수거,점용FPGA적7781개LE(Logic element)화8976 bit존저기,구유량호적확전성.
    The transfer function and the multiple-add calculation of MLP (multilayer perceptron) neural networks are implemented by using the CORDIC(Coordinate rotation digital computer) algorithm and the distributed algorithm. A MLP neural network for function approximation without the required multipliers is constructed through module reuses. The performance of the neural networks is tested on the Nois II platform. Results show that the network using 7781 LEs and 8976 bit memory of the FPGA has an output rate of 17 clocks per data and good expansibility.
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