CAJ | 학술논문

介绍了一种基于0.35 μm GeSi-BiCMOS工艺的1 GSPS采样/保持电路.该电路采用全差分开环结构,使用局部反馈提高开环缓冲放大器的线性度;采用增益、失调数字校正电路补偿高频输入信号衰减和工艺匹配误差造成的失调.在1 GS/s采样率、484.375 MHz输入信号频率、3.3 V电源电压下进行仿真.结果显示,电路的SFDR达到75.6 dB,THD为-74.9 dB,功耗87 mW.将该采样/保持电路用于一个8位1 GSPS A/D转换器.流片测试结果表明,在1 GSPS采样率,240.123 MHz和5.123 MHz输入信号下,8位A/D转换器的SNR为41.39 dB和43.19 dB.
개소료일충기우0.35 μm GeSi-BiCMOS공예적1 GSPS채양/보지전로.해전로채용전차분개배결구,사용국부반궤제고개배완충방대기적선성도;채용증익、실조수자교정전로보상고빈수입신호쇠감화공예필배오차조성적실조.재1 GS/s채양솔、484.375 MHz수입신호빈솔、3.3 V전원전압하진행방진.결과현시,전로적SFDR체도75.6 dB,THD위-74.9 dB,공모87 mW.장해채양/보지전로용우일개8위1 GSPS A/D전환기.류편측시결과표명,재1 GSPS채양솔,240.123 MHz화5.123 MHz수입신호하,8위A/D전환기적SNR위41.39 dB화43.19 dB.
Based on 0.35 μm GeSi-BiCMOS process, a 1 GSPS track-hold circuit with fully differential open-loop structure was designed. In this circuit, local feedback was used to improve linearity of output buffer amplifier, and gain and offset error calibration circuit were adopted to compensate input signal attenuation in high frequency and offset voltage induced by process mismatch. Simulated at 1 GSPS sampling rate, 484.375 MHz analog input signal frequency and 3.3 V supply voltage, the circuit had a spurious-free dynamic range (SFDR) of 75.6 dB and a total harmonic distortion (THD) of -74.9 dB, with 87 mW of power. The track-hold circuit was used in an 8-bit 1 GSPS A/D converter, which had an SNR of 41.39 dB and 43.19 dB at input signal frequency of 240.123 MHz and 5.123 MHz, respectively.