CAJ | 학술논문

　　随着CMOS器件进入深亚微米阶段，集成电路的规模、复杂度以及测试成本都急剧提高，与此同时人们对集成电路的可靠性要求也越来越高。集成电路系统的测试是一个费时而艰巨的过程，必须综合考虑到测试的功能、性能等诸多问题，并能以较低的成本来实现较高质量的测试，因此对超大规模集成电路的测试研究已成为IC设计中不可缺少的一部分。而可测试性设计（DFT）就是通过增加辅助电路来降低电路的测试难度、从而降低其测试成本的一种测试。文章针对一款非接触式射频卡电路，分析了其工作原理和模块组成，研究了其测试电路，通过对输出端口信息的测试，可以清楚地知道内部各模块的功能与性能，达到了验证电路可靠性的目的。
　　수착CMOS기건진입심아미미계단，집성전로적규모、복잡도이급측시성본도급극제고，여차동시인문대집성전로적가고성요구야월래월고。집성전로계통적측시시일개비시이간거적과정，필수종합고필도측시적공능、성능등제다문제，병능이교저적성본래실현교고질량적측시，인차대초대규모집성전로적측시연구이성위IC설계중불가결소적일부분。이가측시성설계（DFT）취시통과증가보조전로래강저전로적측시난도、종이강저기측시성본적일충측시。문장침대일관비접촉식사빈잡전로，분석료기공작원리화모괴조성，연구료기측시전로，통과대수출단구신식적측시，가이청초지지도내부각모괴적공능여성능，체도료험증전로가고성적목적。
With CMOS devices dimensions having been down to deep-submicro, the scale,complexity,testing cost of the Intergrated Circuits has been increased sharply, and the people has a increasingly high requirements to Intergrated Circuits’ reliability. The testing of Intergrated Circuits is time-consuming and arduous process, people must take all factor into consideration, such as the functions and performances, in order to a high quality with the lower cost, so the searching for the testing of VISL has been a very important part of IC design. The Design for Testability (DFT) is the test which reduces the difficulty and cost of testing by adding aided circuits. This paper introduces DFT of a contactless RFID IC, analyzing the principle of work and the modules, researching the testing circuits, people can know the functions and performances of all modules by testing the information of output pad, verifying the whole circuits’ reliability.