CAJ | 학술논문

为了快速地发现SoC性能的瓶颈、实现通信结构的决策，提出一种在事务级采用SystcmC构建片上总线SoC模型的方法。该方法利用端口来连接模块和通道，利用通道来实现接口中定义的方法。经仿真验证，时序完全符合AHB标准，运行速度远高于RTL下的同类模型。该方法有助于在设计流程的早期找寻最优化的片上总线通信结构。
위료쾌속지발현SoC성능적병경、실현통신결구적결책，제출일충재사무급채용SystcmC구건편상총선SoC모형적방법。해방법이용단구래련접모괴화통도，이용통도래실현접구중정의적방법。경방진험증，시서완전부합AHB표준，운행속도원고우RTL하적동류모형。해방법유조우재설계류정적조기조심최우화적편상총선통신결구。
In order to find the bottleneck of the SoC＇ s performance and make a strategic decision for communication architecture, a modeling of transaction level for SoC using SystemC was introduced. The main idea of this method was that the modules were connected to the channels through the ports and the methods in the interfaces were implemented through the channels. The experimental results revealed that the bus model was completely compliant to AHB specification. The rapidity of modeling running under transaction level was higher than that of under register transfer level. This method would help to look for the ideal communication architecture of the chip bus in the early of the design.