黑龙江科技学院学报
黑龍江科技學院學報
흑룡강과기학원학보
JOURNAL OF HEILONGJIANG INSTITUTE OF SCIENCE & TECHNOLOGY
2011年
5期
404-407
,共4页
双斜率积分ADC%开关电容积分器%折叠共源共栅
雙斜率積分ADC%開關電容積分器%摺疊共源共柵
쌍사솔적분ADC%개관전용적분기%절첩공원공책
dual-slope integration AD converter%switched capacitor integrator%folded cascode
为提高双斜率积分ADC中模拟输入信号转换成数字信号的准确性,设计了一种高性能开关电容积分器以替代传统的RC有源积分器。该开关电容积分器的运算放大器由折叠共源共栅输入级和Class AB输出级组成,开关部分选用CMOS开关,以抑制电荷注入和时钟馈通的影响。在中芯国际0.18μmCMOS工艺下,采用EDA仿真软件对相关模块进行仿真验证,得到运算放大器的直流增益为110.3 dB,单位增益带宽为5.64 MHz,相位裕度达到79°,输出摆幅为0.013 3~3 299 mV,转换速率为7.56 MV/s。结果表明,开关电容积分器完全满足双斜率积分ADC的实际应用。
為提高雙斜率積分ADC中模擬輸入信號轉換成數字信號的準確性,設計瞭一種高性能開關電容積分器以替代傳統的RC有源積分器。該開關電容積分器的運算放大器由摺疊共源共柵輸入級和Class AB輸齣級組成,開關部分選用CMOS開關,以抑製電荷註入和時鐘饋通的影響。在中芯國際0.18μmCMOS工藝下,採用EDA倣真軟件對相關模塊進行倣真驗證,得到運算放大器的直流增益為110.3 dB,單位增益帶寬為5.64 MHz,相位裕度達到79°,輸齣襬幅為0.013 3~3 299 mV,轉換速率為7.56 MV/s。結果錶明,開關電容積分器完全滿足雙斜率積分ADC的實際應用。
위제고쌍사솔적분ADC중모의수입신호전환성수자신호적준학성,설계료일충고성능개관전용적분기이체대전통적RC유원적분기。해개관전용적분기적운산방대기유절첩공원공책수입급화Class AB수출급조성,개관부분선용CMOS개관,이억제전하주입화시종궤통적영향。재중심국제0.18μmCMOS공예하,채용EDA방진연건대상관모괴진행방진험증,득도운산방대기적직류증익위110.3 dB,단위증익대관위5.64 MHz,상위유도체도79°,수출파폭위0.013 3~3 299 mV,전환속솔위7.56 MV/s。결과표명,개관전용적분기완전만족쌍사솔적분ADC적실제응용。
Aimed at improving the accuracy of the analog-digital conversion in dual-slope ADCs,this paper introduces a high-performance switched-capacitor integrator to replace the conventional active RC integrator.The operation amplifier in this switched-capacitor integrator is composed of a folded cascade input stage and a Class AB output stage and CMOS switches are utilized to suppress charge injection and clock feed-through effects.The simulation of all the circuit modules by EDA simulation software,depending on SMIC 0.18 μm CMOS process,shows that the operation amplifier is capable of a DC gain of 110.3 dB,a unity gain bandwidth of 5.64 MHz,a phase margin of 79°,an output swing of 0.013 3-3 299 mV,and a slew rate of 7.56 MV/s.The switched-capacitor integrator proves quite suitable for the practical applications in the dual-slope ADCs.