CAJ | 학술논문

首次在国内成功地制作了栅长为70nm的高性能CMOS器件．为了抑制70nm器件的短沟道效应同时提高它的驱动能力，采用了一些新的关键工艺技术，包括3nm的氮化栅氧化介质，多晶硅双栅电极，采用重离子注入的超陡倒掺杂沟道剖面，锗预无定形注入加低能注入形成的超浅源漏延伸区，以及锗预无定形注入加特殊清洗处理制备薄的、低阻自对准硅化物等．CMOS器件的最短的栅长(即多晶硅栅条宽度)只有70nm，其NMOS的阈值电压、跨导和关态电流分别为0.28V、490mS/m和0.08nA／μm；而PMOS阈值电压、跨导和关态电流分别为－0.3V、340mS／mm和0.2nA／μm．并研制成功了100nm栅长的CMOS57级环形振荡器，其在1.5V、2V和3V电源电压下的延迟分别为23.5ps/级、17.5ps/级和12.5ps/级．
수차재국내성공지제작료책장위70nm적고성능CMOS기건．위료억제70nm기건적단구도효응동시제고타적구동능력，채용료일사신적관건공예기술，포괄3nm적담화책양화개질，다정규쌍책전겁，채용중리자주입적초두도참잡구도부면，타예무정형주입가저능주입형성적초천원루연신구，이급타예무정형주입가특수청세처리제비박적、저조자대준규화물등．CMOS기건적최단적책장(즉다정규책조관도)지유70nm，기NMOS적역치전압、과도화관태전류분별위0.28V、490mS/m화0.08nA／μm；이PMOS역치전압、과도화관태전류분별위－0.3V、340mS／mm화0.2nA／μm．병연제성공료100nm책장적CMOS57급배형진탕기，기재1.5V、2V화3V전원전압하적연지분별위23.5ps/급、17.5ps/급화12.5ps/급．
A high performance 70nm CMOS device has been demonstrated for thefirst time in the continent， China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly-Si gate electrode, novel super-steep retrograde channel doping by heavy ion implantation, ultra-shallow S/D extension formed by Ge PAI(Pre-Amorphism Implantation) plus LEI（Low Energy Implantation）, thin and low resistance Ti-SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages，Gm and off current are 0.28V，490mS．mm－1 and 0.08nA/μm for NMOS and -0.3V，340mS*mm－1 and 0.2nA/μm for PMOS, respectively. Delays of 23.5ps/stage at 1.5V, 17.5ps/stage at 2.0V and 12.5ps/stage at 3V are achieved in the 57-stage unloaded 100nm CMOS ring oscillator circuits.