CAJ | 학술논문

研究基于DDS(直接数字频率合成)的任意波信号产生的机理,在FPGA内嵌SOPC,配置了32位的软微处理器NiosII,利用FPGA实现双DDS的相位累加器,通过数字方法直接实现任意波形的各种频率调制.分析了高速相位累加器截断误差,幅度量化误差和D/A非线性引起的杂散分量产生的原因.推导出DDS相位噪声模型,针对信号的频谱成份设计了高阶低通滤波器对输出信号滤波.结合NiosII,设计硬件电路对输出信号进行幅频校正,保证了信号幅值的稳定输出及实际显示数值的一致性.测试表明,信号波形发生器能输出稳定、高带宽、高速度、高精度、低衰减的任意波形,三角波的输出频率大于1 MHz,输出信号幅度峰峰值在50 mV～20 V范围内以10 mV的步进调节.
연구기우DDS(직접수자빈솔합성)적임의파신호산생적궤리,재FPGA내감SOPC,배치료32위적연미처리기NiosII,이용FPGA실현쌍DDS적상위루가기,통과수자방법직접실현임의파형적각충빈솔조제.분석료고속상위루가기절단오차,폭도양화오차화D/A비선성인기적잡산분양산생적원인.추도출DDS상위조성모형,침대신호적빈보성빈설계료고계저통려파기대수출신호려파.결합NiosII,설계경건전로대수출신호진행폭빈교정,보증료신호폭치적은정수출급실제현시수치적일치성.측시표명,신호파형발생기능수출은정、고대관、고속도、고정도、저쇠감적임의파형,삼각파적수출빈솔대우1 MHz,수출신호폭도봉봉치재50 mV～20 V범위내이10 mV적보진조절.
In this paper, the principle of arbitrary wave generator based on DDS is studied; one 32-bit NiosII soft-core is embedded in an FPGA. Dual DDS phase accumulator is designed, through digital method different frequency modulations of arbitrary wave are implemented. The errors caused by phase truncation, amplitude quantization and nonlinear properties of D/A are analyzed, and then a phase noise model is deduced, a high-order low pass filter is designed according to the signal frequency spectrum. Combined with NiosII, a hardware correction circuit is designed to adjust the amplitude in different frequency bands, which guarantees the amplitude output and the consistency between the amplitude output and the displayed value in LCD. Final test shows that the wave generator can produce stable, high bandwidth, high speed, high precision and low attenuation arbitrary waves. The frequency of triangular wave is above 1 MHz, and the peak-peak amplitude of the output signal can be adjusted in a range from 50 mV to 20 V with a minimum step of 10 mV.