CAJ | 학술논문

将能量回收技术应用于灵敏放大器型D触发器(SAERD),该电路采用单相正弦时钟,用来回收时钟端的能量,对于触发器的内部节点和存储单元仍采用恒定电源.在时钟频率为100～300 MHz时.时钟端的功耗较输入方波时平均节省约80%.在SMIC 0.13 μm工艺下将SAERD应用于一款函数发生器,并与传统主从型D触发器(MSD)实现的电路进行功耗比较.仿真结果显示,时钟频率为200 MHz时,功耗节省高达17.1%.
장능량회수기술응용우령민방대기형D촉발기(SAERD),해전로채용단상정현시종,용래회수시종단적능량,대우촉발기적내부절점화존저단원잉채용항정전원.재시종빈솔위100～300 MHz시.시종단적공모교수입방파시평균절성약80%.재SMIC 0.13 μm공예하장SAERD응용우일관함수발생기,병여전통주종형D촉발기(MSD)실현적전로진행공모비교.방진결과현시,시종빈솔위200 MHz시,공모절성고체17.1%.
A sense amplifier D flip-flop using energy recovery, SAERD (sense amplifier energy recovery D flip-flop), was presented. The flip-flops proposed operate with a single-phase sinusoidal clock to recycle the energy of the clock pad while the internal nodes and storage elements are powered by constant supply. The power consumption of the clock pad is saving 80 % on average as compared to the same implementation using the square-wave clock scheme for clock rates ranging from 100 to 300 MHz. In the SMIC 0.13 μm CMOS technology, a function generator is implemented using SAERD. Simulation result shows a total power saving of up to 17.1% as compared to the implementation using the conventional D flip-flops MSD (master salve D flipflop).