CAJ | 학술논문

给出了一种GF(256)域上的RS(204，188)码编码器的实现算法，建立了C语言行为级模型和RTL级硬件模型。采用了具有对称系数的生成多项式，减少了有限域乘法器的个数。通过逻辑综合、优化得到了电路网表与FPGA网表，并进行了二者的仿真验证。该电路的规模约为4100门左右，约为一般的该编码器70％。
급출료일충GF(256)역상적RS(204，188)마편마기적실현산법，건립료C어언행위급모형화RTL급경건모형。채용료구유대칭계수적생성다항식，감소료유한역승법기적개수。통과라집종합、우화득도료전로망표여FPGA망표，병진행료이자적방진험증。해전로적규모약위4100문좌우，약위일반적해편마기70％。
This paper describes the arithmetic to implement RS (204,188) encoder on GF (256). A behavior model described by C language and a RTL hardware model has been established. This encoder has adopted symmetrical coefficients in order to reduce the multipliers of finite field. The circuit net and FPGA net have been achieved by logic synthesis and optimize technology. These nets are simulated and validated,furthermore. The circuit scale of encoder that has been synthesized is about 4100 gates. Its frequency is up to 35MHz,and its scale is about 70% of the ordinary encoder.