上海大学学报（英文版）
上海大學學報（英文版）
상해대학학보（영문판）
JOURNAL OF SHANGHAI UNIVERSITY (ENGLISH EDITION)
2008年
5期
450-456
,共7页
高艳霞%郭水保%LIN-SHI Xue-fang%ALLARD Bruno
高豔霞%郭水保%LIN-SHI Xue-fang%ALLARD Bruno
고염하%곽수보%LIN-SHI Xue-fang%ALLARD Bruno
digital control%digital pulse-width modulation (DPWM)%limit cycle%buck converter
This paper models a low-power high-frequency digitally controlled synchronous rectifier (SR) buck converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation (DPWM) and steady-state limit cycles of digital control switching model power supply (SMPS) are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.
