重庆邮电大学学报（自然科学版）
重慶郵電大學學報（自然科學版）
중경유전대학학보（자연과학판）
JOURNAL OF CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS(NATURAL SCIENCE EDITION)
2010年
2期
209-213
,共5页
CMOS%两级%运算放大器%电源抑制比
CMOS%兩級%運算放大器%電源抑製比
CMOS%량급%운산방대기%전원억제비
CMOS%two-stage%operational amplifier( op-amp}%power-supply rejection ratio(PSRR)
在解释了传统基本两级CMOS运算放大器低电源抑制比(PSRR)原因的基础上,提出了一种简单电路技术来提高传统基本两级CMOS运算放大器中频PSRR.该方法原理是通过改变偏置结构产生一个额外的信号支路在输出端跟随电源增益,这样在输出端可以得到近似为零的电源纹波增益,从而能提高运放的PSRR.采用0.35μm标准CMOS工艺库,在Cadence环境下仿真结果显示,改进的运算放大器的PSRR在中频范围内比传统运算放大器可提高20 dB以上.
在解釋瞭傳統基本兩級CMOS運算放大器低電源抑製比(PSRR)原因的基礎上,提齣瞭一種簡單電路技術來提高傳統基本兩級CMOS運算放大器中頻PSRR.該方法原理是通過改變偏置結構產生一箇額外的信號支路在輸齣耑跟隨電源增益,這樣在輸齣耑可以得到近似為零的電源紋波增益,從而能提高運放的PSRR.採用0.35μm標準CMOS工藝庫,在Cadence環境下倣真結果顯示,改進的運算放大器的PSRR在中頻範圍內比傳統運算放大器可提高20 dB以上.
재해석료전통기본량급CMOS운산방대기저전원억제비(PSRR)원인적기출상,제출료일충간단전로기술래제고전통기본량급CMOS운산방대기중빈PSRR.해방법원리시통과개변편치결구산생일개액외적신호지로재수출단근수전원증익,저양재수출단가이득도근사위령적전원문파증익,종이능제고운방적PSRR.채용0.35μm표준CMOS공예고,재Cadence배경하방진결과현시,개진적운산방대기적PSRR재중빈범위내비전통운산방대기가제고20 dB이상.
On the basis of explaining low power-supply rejection ratio (PSRR) of the traditional basic two-stage CMOS operational amplifier (op-amp), a simple circuit technique is presented for improving poor midband PSRR of the traditional basic two-stage CMOS single ended op-amp. The principle of the technique is to create an additional parallel signal path to follow signal gain from the power-supply to the output by means of changing the bias structure, which produces almost zero power-supply ripple gain through the output stage and improves the PSRR. Cadence simulation results of a proposed two-stage op-amp based on standard 0.35 μm technology show that more than 20 dB improvement in the midband PSRR is obtainable compared with a traditional basic two-stage op-amp without the suggested circuit.
