上海大学学报（英文版）
上海大學學報（英文版）
상해대학학보（영문판）
JOURNAL OF SHANGHAI UNIVERSITY (ENGLISH EDITION)
2006年
5期
425-430
,共6页
Ethernet passive optical network%broadband access%field programmable gate array%embedded system
This paper presents the design and implementation of access controller used for Ethernet passive optical network (EPON).As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array (FPGA) with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.
