CAJ | 학술논문

For the conventional single-ended eFuse cell,sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms.A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell.Also,a sensing circuit of sense amplifier is proposed,based on D flip-flop structure to implement a simple sensing circuit.Furthermore,a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse.When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC,the layout dimensions are 229.04 μm × 100.15 μm.All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.