CAJ | 학술논문

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进，主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面，它有效地减小了器件的基区面积．测试结果表明，晶体管有良好的交直流特性．在发射区面积为3μm×8μm时，晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps，硅微波静态二分频器的工作频率为3.2GHz．
보도료쌍층다정규발사겁초고속정체관급전로적공예연구．저충결구시재단층다정규발사겁정체관공예기출상진행료다항개진，주요집중재제일층다정규적수직각식화기구、발사구지간적양화규、담화규복합개질적L형측장형성기술방면，타유효지감소료기건적기구면적．측시결과표명，정체관유량호적교직류특성．재발사구면적위3μm×8μm시，정체관적절지빈솔위6.1GHz．19급배진평균문연지소우40ps，규미파정태이분빈기적공작빈솔위3.2GHz．
The fabrication of the very high speed polysilicon emitter bipolar transistors and circuit with double-layer polysilicon has been reported.This kind of structure has been improved in many aspects compared with the single-layer polysilicon emitter bipolar transistors,especially in the vertical dry etch of the first polysilicon and the technology to form the multiple-dielectric-layers L-shaped sidewall,consisting of SiO2 and Si3N4 between the base and the emitter.It effectively reduces the base area of the bipolar transistor.The good DC,AC performance and cutoff frequency of 6.1GHz have been obtained in the emitter size of 3μm×8μm.The minimum gate delay of 19-stage ECL ring oscillator is 40ps/gate and the maximum toggle frequency of a　2∶1 static divider is 3.2GHz.