CAJ | 학술논문

提出了一种符合ISO/IEC 18000-6B标准的无源UHF RFID电子标签验证开发平台,其工作在915MHz ISM频带下.该平台有效减少了设计开发时间及成本,并实现了电子标签的快速原型设计.该平台包括RFID模拟前端以及采用Altera ACEX FPGA实现的标签控制逻辑.RFID模拟前端采用Chartered 0.35μm 2P4M CMOS工艺进行流片,包括本地振荡器、时钟产生电路、复位电路、匹配网络和反向散射电路、整流器、稳压器以及AM解调器等,通过调整FPGA中的标签控制逻辑,该平台实现了快速、灵活而高效的RFID验证开发.
제출료일충부합ISO/IEC 18000-6B표준적무원UHF RFID전자표첨험증개발평태,기공작재915MHz ISM빈대하.해평태유효감소료설계개발시간급성본,병실현료전자표첨적쾌속원형설계.해평태포괄RFID모의전단이급채용Altera ACEX FPGA실현적표첨공제라집.RFID모의전단채용Chartered 0.35μm 2P4M CMOS공예진행류편,포괄본지진탕기、시종산생전로、복위전로、필배망락화반향산사전로、정류기、은압기이급AM해조기등,통과조정FPGA중적표첨공제라집,해평태실현료쾌속、령활이고효적RFID험증개발.
This paper introduces a novel verification development platform for the passive UHF RFID tag,which is compatible with the ISO/IEC 18000-6B standard,operating in the 915MHz ISM band.This platform efficiently reduces the design and development time and cost,and implements a fast prototype design of the passive UHF RFID tag.It includes the RFID analog front end and the tag control logic,which is implemented in an Altera ACEX FPGA.The RFID analog front end,which is fabricated using a Chartered 0.35μm two-poly four-metal CMOS process,contains a local oscillator,power on reset circuit,matching network and backscatter,rectifier,regulator,AM demodulator,etc.The platform achieves rapid,flexible and efficient verification and development,and can also be fit for other RFID standards after changing the tag control logic in FPGA.