CAJ | 학술논문

采用0.13 μm标准CMOS工艺,全定制设计实现了一款8 kB(8 k*8 bit)的高速低功耗静态随机存取存储器(SRAM).分析了影响存储器性能和功耗的原因,并在电路布局上做了改进,将两个3-8译码器进行拆分与重组,降低了互连线的延迟和耦合作用;同时,对灵敏放大器也做了改进.版图后仿真表明,在电源电压为1.2 V、温度为25 ℃的典型条件下,读1延时为766.37 ps,最大功耗为11.29 mW,功耗延时积PDP为8.65 pJ,实现了很好的性能.
채용0.13 μm표준CMOS공예,전정제설계실현료일관8 kB(8 k*8 bit)적고속저공모정태수궤존취존저기(SRAM).분석료영향존저기성능화공모적원인,병재전로포국상주료개진,장량개3-8역마기진행탁분여중조,강저료호련선적연지화우합작용;동시,대령민방대기야주료개진.판도후방진표명,재전원전압위1.2 V、온도위25 ℃적전형조건하,독1연시위766.37 ps,최대공모위11.29 mW,공모연시적PDP위8.65 pJ,실현료흔호적성능.
A fully customized high-speed and low-power 8 kB SRAM was designed and implemented using 0.13 μm standard CMOS process.Factors affecting performance and power of SRAM were analyzed.And the circuit layout was improved.By splitting and regrouping two 3-8 decoders, the delay and coupling of interconnected wire were shortened and improved, as well as sense-amplifier.Results from post-layout simulation showed that, at 1.2 V supply and 25 ℃, the circuit has a read-one delay of 766.37 ps, a maximum power of 11.29 mW, and a power-delay product (PDP) of 8.65 pJ.