CAJ | 학술논문

提出了一种基于Boonsobhak结构但电源效率更高的开关电流比较器.比较器采用主从式结构,工作模式由两相不交叠时钟控制.主比较器根据输入电流信号的极性产生微小电压差,同时将输出信号对输入信号的影响隔离开来.从比较器将主比较器产生的微小电压差进行再生放大,最终产生比较结果.提出的新比较器结构采用静态甲乙类锁存式比较器作为主比较器,以静态功耗为零的动态锁存式比较器为从比较器,使得整体比较器在保持较高速度的同时,功耗大为降低.采用CSMC 0.6 μm CMOS工艺设计并实现,实际测试结果显示开关电流比较器具有6.5 bit分辨率,能在20 MHz时钟频率下正常工作,而功耗降低了75%.
제출료일충기우Boonsobhak결구단전원효솔경고적개관전류비교기.비교기채용주종식결구,공작모식유량상불교첩시종공제.주비교기근거수입전류신호적겁성산생미소전압차,동시장수출신호대수입신호적영향격리개래.종비교기장주비교기산생적미소전압차진행재생방대,최종산생비교결과.제출적신비교기결구채용정태갑을류쇄존식비교기작위주비교기,이정태공모위령적동태쇄존식비교기위종비교기,사득정체비교기재보지교고속도적동시,공모대위강저.채용CSMC 0.6 μm CMOS공예설계병실현,실제측시결과현시개관전류비교기구유6.5 bit분변솔,능재20 MHz시종빈솔하정상공작,이공모강저료75%.
A power efficiency improved switched current comparator based on Boonsobhak's comparator is presented. Controlled by two complementary clock signals, the proposed comparator operates in a master and slave manner. The master comparator not only generates a voltage difference according to the input current, but also isolates the input terminal from the output signals to prevent extreme voltage surge, or kickback noise, while the slave comparator is allowed to regenerate and produce a valid digital output. Employing a static class AB latched comparator as the master comparator and a 0-static-power-dissipated dynamic latched comparator as the slave one, the proposed current comparator achieves high power efficiency and high speed. Designed and simulated in CSMC 0.6 μm CMOS technology with 5 V supply voltage, the measurements show that the proposed SI comparator achieves a resolution of 6.5 bits, and works well at 20 MHz sampling frequency with 75% power reduction compared to the original.