科技广场
科技廣場
과기엄장
SCIENCE TECHNOLOGY PLAZA
2011年
5期
142-145
,共4页
混沌序列%可编程门阵列%伪随机序列
混沌序列%可編程門陣列%偽隨機序列
혼돈서렬%가편정문진렬%위수궤서렬
Chaotic Sequences%FPGA%Pseudo-random Sequences
针对现有的PRNG的均匀性差的特性,文献[1]提出了一种将混沌序列变换成均匀伪随机序列的普适算法。我们首次提出该算法的FPGA实现方案,方案由上位机软件、UART控制器、初值缓存器、均匀化算法实现单元、尾数序列缓存转换器组成。采用VHDL完成各模块设计,芯片选用逻辑资源为100万门的CycloneIIEP2C35F672C6,硬件电路共占6721逻辑单元,资源率20%,工作频率为50MHz。
針對現有的PRNG的均勻性差的特性,文獻[1]提齣瞭一種將混沌序列變換成均勻偽隨機序列的普適算法。我們首次提齣該算法的FPGA實現方案,方案由上位機軟件、UART控製器、初值緩存器、均勻化算法實現單元、尾數序列緩存轉換器組成。採用VHDL完成各模塊設計,芯片選用邏輯資源為100萬門的CycloneIIEP2C35F672C6,硬件電路共佔6721邏輯單元,資源率20%,工作頻率為50MHz。
침대현유적PRNG적균균성차적특성,문헌[1]제출료일충장혼돈서렬변환성균균위수궤서렬적보괄산법。아문수차제출해산법적FPGA실현방안,방안유상위궤연건、UART공제기、초치완존기、균균화산법실현단원、미수서렬완존전환기조성。채용VHDL완성각모괴설계,심편선용라집자원위100만문적CycloneIIEP2C35F672C6,경건전로공점6721라집단원,자원솔20%,공작빈솔위50MHz。
Aiming at the poor uniformity of existing PRNG,literature[1] presents a universal algorithm for transforming chaotic sequences of either chaotic map systems or chaotic differentrial dynamic systems into uniform pseudo-random sequences.We present a scheme for FPGA implementation of the algorithm at the first time.This scheme consist of upper computer software,UART Controller,initial value buffer,uniformization algorithm implementation unit and mantissa sequence transformer.Using CycloneII EP2C35F672C6 chip with one million gates,The design is with every block implementation in VHDL and the system hardware circuit occupies 6721 logical elements,accounting for 20% chip resources under a running condition of 50 MHZ.
