基于FPGA的细粒度并行K-means算法加速器的设计与实现
기우FPGA적세립도병행K-means산법가속기적설계여실현
Fine-Grained Parallel K-means Clustering Algorithm on FPGA
  • 万方数据
    计算机工程与科学 계산궤공정여과학
    COMPUTER ENGINEERING & SCIENCE
    2009年 z1期 64-67 ,共4页

    倪时策%窦勇%雷元武%赵建勋

    예시책%두용%뢰원무%조건훈

    K-means算法%FPGA%硬件加速器%浮点实现 K-means算法%FPGA%硬件加速器%浮點實現
    K-means산법%FPGA%경건가속기%부점실현
    K-means algorithm%FPGA%hardware accelerator%float point
    本文在深入分析K-means算法计算特征的基础上,基于FPGA平台提出并实现了一种细粒度的并行浮点K-means算法.设计采用了阵列多PE并行处理的任务划分策略,实现了处理单元间的负载平衡,采用数据驱动的流水线隐藏片外存储访问,设计了一种基于脉动阵列结构的主从多PE并行计算阵列,并在单片FPGA(XC5VLX330)上成功集成了4个PE.实验结果表明,我们提出的K-means算法加速器结构具备良好的可扩展性.通过实验测试,我们的实现方案相对于Pentium 4 2.66 GHz 单处理器程序达到了15倍的加速比.
    본문재심입분석K-means산법계산특정적기출상,기우FPGA평태제출병실현료일충세립도적병행부점K-means산법.설계채용료진렬다PE병행처리적임무화분책략,실현료처리단원간적부재평형,채용수거구동적류수선은장편외존저방문,설계료일충기우맥동진렬결구적주종다PE병행계산진렬,병재단편FPGA(XC5VLX330)상성공집성료4개PE.실험결과표명,아문제출적K-means산법가속기결구구비량호적가확전성.통과실험측시,아문적실현방안상대우Pentium 4 2.66 GHz 단처리기정서체도료15배적가속비.
    We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA. We partition tasks by rows and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load data from external memory. To our knowledge, our implementation with 4 PEs is the only FPGA accelerator(XC5VLX330) implementing the complete K-means clustering algorithm. The experimental results show a factor of more than 15 speedup over the Cluster 3.0 software running on a PC platform with Pentium 4 2.66GHz CPU.
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